Electronics & TPC

    Electronics in LAr

    The commonly referred BNL "cold electronics" is a custom designed complementary metal-oxide-semiconductor (CMOS) analog front-end cold application-specfic integrated circuit (ASIC) operated in the LAr to amplify and shape the induced current from each wire from LArTPC. Compared to the warm electronics, the cold electronics has the advantage to be placed at the wire in order to minimize the overall capacitance. In addition, the noise level measured in equivalent noise charge is much lower for the CMOS technology at the low temperature. Due to lack of amplification of electrons inside LAr, the low noise with the cold electronics is essential to reliable extract ionization electron signal from both the collection and induction wire planes in a single-phase LArTPC. The current development of the cold electronics lies on the cold ADC and cold signal multiplexing. The integration of these capabilities in the cold LAr would minimize the signal penetrations on the 10 kt LArTPC cryostat designed for DUNE.

    The level of noise from the entire electronic readout chain is expressed as the Equivalent Noise Charge (ENC) measured in units of number of electrons. The ENC is defined as the number of instantaneously collected electrons required so that their peak ADC count is equal to the root mean square (RMS) value of the noise measured also in ADC. The ENC from the noise sources listed above can be approximated by a simple formula \[ {ENC}^2 \approx {\frac{1}{2} {A_1} \frac{{e^2_n}{C^2_{in}}} {t_p}} + {A_2 \pi C_{in}^2 A_f} + {A_3 \left(q_e I_o + \frac {2 k_B T} {R_b}\right) t_p} \label{eq:ENC} \] The first two terms represent the input transistor noise (white and $1/f$ series). Here $C_{in}$ is the total capacitance at the input of the ASIC which includes that of the sense wire, the leads, their connections to the ASIC and the input transistor gate capacitance. The $e_n$ is the white series noise spectral density in the unit of V/Hz. The series $1/f$ noise spectral density in V/Hz is given by $\sqrt{A_f/f}$. Both $e_n$ and $A_f$ are determined from the ASIC's input p-channel metal-oxide semiconductor (pMOS) transistor measurements and depend on the transistor technology and transistor design. The two components in the third term represent white parallel noise, arising from the ASIC bias current, $I_o$ (shot noise) and the wire bias resistor (thermal noise), where $k_B$ is the Boltzman constant, $q_e$ is electron charge, $T$ is temperature and $R_b$ is the wire bias resistor. The $t_p$ is the peaking time of the anti-aliasing filter.


    Useful formulas for design of TPCs with multiple parallel wire planes are derived by Dr. G. Horton-Smith using an extension of conformal representation theory previously applied to single-grid ionization chambers [2]. Expressions are given for the electric potential and field lines around the wires, the fraction of electrons collected by the wire planes, and the relation between wire plane voltages and asymptotic fields between planes. Python code for calculating and plotting potentials for DUNE situation is provided. The result (right plot) is consistent with that of Finite Element Model (FEM) calculation.


    1. Veljko Radeka et al. "Cold electronics for Giant Liquid Argon Time Projection Chambers", J. Phys. Conf. Ser., 308:012021, 2011..
    2. G. Horton-Smith, "Wire Plane Analytic Calculations", MicroBooNE doc:4708